#ifndef __STM32H743VIT6_IRQ_NUM_H__
#define __STM32H743VIT6_IRQ_NUM_H__


#define  RESET_IRQNUM                    1
#define  NMI_IRQNUM                      2
#define  HARD_FAULT_IRQNUM               3
#define  MEM_MANAGER_IRQNUM              4
#define  BUS_FAULT_IRQNUM                5
#define  USAGE_FAULT_IRQNUM              6
#define  SVC_IRQNUM                      11
#define  DEBUG_BUGMON_IRQNUM             12
#define  PENDSV_IRQNUM                   14
#define  SYSTICK_IRQNUM                  15
#define  WWDG_IRQNUM                     16  /* Window WatchDog              */
#define  PVD_IRQNUM                      17  /* PVD/AVD through EXTI Line detection */
#define  TAMPER_IRQNUM                   18  /* Tamper and TimeStamps through the EXTI line */
#define  RTC_IRQNUM                      19  /* RTC Wakeup through the EXTI line */
#define  FLASH_IRQNUM                    20  /* FLASH                        */
#define  RCC_IRQNUM                      21  /* RCC                          */
#define  EXTI0_IRQNUM                    22  /* EXTI Line0                   */
#define  EXTI1_IRQNUM                    23  /* EXTI Line1                   */
#define  EXTI2_IRQNUM                    24  /* EXTI Line2                   */
#define  EXTI3_IRQNUM                    25  /* EXTI Line3                   */
#define  EXTI4_IRQNUM                    26  /* EXTI Line4                   */
#define  DMA1_CH0_IRQNUM                 27  /* DMA1 Stream 0                */
#define  DMA1_CH1_IRQNUM                 28  /* DMA1 Stream 1                */
#define  DMA1_CH2_IRQNUM                 29  /* DMA1 Stream 2                */
#define  DMA1_CH3_IRQNUM                 30  /* DMA1 Stream 3                */
#define  DMA1_CH4_IRQNUM                 31  /* DMA1 Stream 4                */
#define  DMA1_CH5_IRQNUM                 32  /* DMA1 Stream 5                */
#define  DMA1_CH6_IRQNUM                 33  /* DMA1 Stream 6                */
#define  ADC1_2_3_IRQNUM                 34  /* ADC1, ADC2 and ADC3s         */
#define  FDCAN1_IT0_IRQNUM               35  /* FDCAN1 interrupt line 0      */
#define  FDCAN2_IT0_IRQNUM               36  /* FDCAN2 interrupt line 0      */
#define  FDCAN1_IT1_IRQNUM               37  /* FDCAN1 interrupt line 1      */
#define  FDCAN2_IT1_IRQNUM               38  /* FDCAN2 interrupt line 1      */
#define  EXTI9_5_IRQNUM                  39  /* External Line[9:5]s          */
#define  TIM1_BRK_IRQNUM                 40  /* TIM1 Break interrupt         */
#define  TIM1_UP_IRQNUM                  41  /* TIM1 Update interrupt        */
#define  TIM1_TRG_COM_IRQNUM             42  /* TIM1 Trigger and Commutation interrupt */
#define  TIM1_CC_IRQNUM                  43  /* TIM1 Capture Compare         */
#define  TIM2_IRQNUM                     44  /* TIM2                         */
#define  TIM3_IRQNUM                     45  /* TIM3                         */
#define  TIM4_IRQNUM                     46  /* TIM4                         */
#define  I2C1_EV_IRQNUM                  47  /* I2C1 Event                   */
#define  I2C1_ER_IRQNUM                  48  /* I2C1 Error                   */
#define  I2C2_EV_IRQNUM                  49  /* I2C2 Event                   */
#define  I2C2_ER_IRQNUM                  50  /* I2C2 Error                   */
#define  SPI1_IRQNUM                     51  /* SPI1                         */
#define  SPI2_IRQNUM                     52  /* SPI2                         */
#define  USART1_IRQNUM                   53  /* USART1                       */
#define  USART2_IRQNUM                   54  /* USART2                       */
#define  USART3_IRQNUM                   55  /* USART3                       */
#define  EXTI15_10_IRQNUM                56  /* External Line[15:10]s        */
#define  RTC_ALARM_IRQNUM                57  /* RTC Alarm (A and B) through EXTI Line */
#define  TIM8_BRK_TIM12_IRQNUM           59  /* TIM8 Break and TIM12         */
#define  TIM8_UP_TIM13_IRQNUM            60  /* TIM8 Update and TIM13        */
#define  TIM8_TRG_COM_TIM14_IRQNUM       61  /* TIM8 Trigger and Commutation and TIM14 */
#define  TIM8_CC_IRQNUM                  62  /* TIM8 Capture Compare         */
#define  DMA1_CH8_IRQNUM                 63  /* DMA1 Stream7                 */
#define  FMC_IRQNUM                      64  /* FMC                          */
#define  SDMMC1_IRQNUM                   65  /* SDMMC1                       */
#define  TIM5_IRQNUM                     66  /* TIM5                         */
#define  SPI3_IRQNUM                     67  /* SPI3                         */
#define  UART4_IRQNUM                    68  /* UART4                        */
#define  UART5_IRQNUM                    69  /* UART5                        */
#define  TIM6_DAC_IRQNUM                 70  /* TIM6 and DAC1&2 underrun errors */
#define  TIM7_IRQNUM                     71
#define  DMA2_CH0_IRQNUM                 72
#define  DMA2_CH1_IRQNUM                 73
#define  DMA2_CH2_IRQNUM                 74
#define  DMA2_CH3_IRQNUM                 75
#define  DMA2_CH4_IRQNUM                 76
#define  ETH_IRQNUM                      77
#define  ETH_WKUP_IRQNUM                 78
#define  FDCAN_CAL_IRQNUM                79
#define  DMA2_CH5_IRQNUM                 84
#define  DMA2_CH6_IRQNUM                 85
#define  DMA2_CH7_IRQNUM                 86
#define  USART6_IRQNUM                   87
#define  I2C3_EV_IRQNUM                  88
#define  I2C3_ER_IRQNUM                  89
#define  OTG_HS_EP1_OUT_IRQNUM           90
#define  OTG_HS_EP1_IN_IRQNUM            91
#define  OTG_HS_WKUP_IRQNUM              92
#define  OTG_HS_IRQNUM                   93
#define  DCMI_IRQNUM                     94
#define  RNG_IRQNUM                      96
#define  FPU_IRQNUM                      97
#define  UART7_IRQNUM                    98
#define  UART8_IRQNUM                    99
#define  SPI4_IRQNUM                     100
#define  SPI5_IRQNUM                     101
#define  SPI6_IRQNUM                     102
#define  SAI1_IRQNUM                     103
#define  LTDC_IRQNUM                     104
#define  LTDC_ER_IRQNUM                  105
#define  DMA2D_IRQNUM                    106
#define  SAI2_IRQNUM                     107
#define  QUADSPI_IRQNUM                  108
#define  LPTIM1_IRQNUM                   109
#define  CEC_IRQNUM                      110
#define  I2C4_EV_IRQNUM                  111
#define  I2C4_ER_IRQNUM                  112
#define  SPDIF_RX_IRQNUM                 113
#define  OTG_FS_EP1_OUT_IRQNUM           114
#define  OTG_FS_EP1_IN_IRQNUM            115
#define  OTG_FS_WKUP_IRQNUM              116
#define  OTG_FS_IRQNUM                   117
#define  DMAMUX1_OVR_IRQNUM              118
#define  HRTIM1_Master_IRQNUM            119
#define  HRTIM1_TIMA_IRQNUM              120
#define  HRTIM1_TIMB_IRQNUM              121
#define  HRTIM1_TIMC_IRQNUM              122
#define  HRTIM1_TIMD_IRQNUM              123
#define  HRTIM1_TIME_IRQNUM              124
#define  HRTIM1_FLT_IRQNUM               125
#define  DFSDM1_FLT0_IRQNUM              126
#define  DFSDM1_FLT1_IRQNUM              127
#define  DFSDM1_FLT2_IRQNUM              128
#define  DFSDM1_FLT3_IRQNUM              129
#define  SAI3_IRQNUM                     130
#define  SWPMI1_IRQNUM                   131
#define  TIM15_IRQNUM                    132
#define  TIM16_IRQNUM                    133
#define  TIM17_IRQNUM                    134
#define  MDIOS_WKUP_IRQNUM               135
#define  MDIOS_IRQNUM                    136
#define  JPEG_IRQNUM                     137
#define  MDMA_IRQNUM                     138
#define  SDMMC2_IRQNUM                   140
#define  HSEM1_IRQNUM                    141
#define  ADC3_IRQNUM                     143
#define  DMAMUX2_OVR_IRQNUM              144
#define  BDMA_Channel0_IRQNUM            145
#define  BDMA_Channel1_IRQNUM            146
#define  BDMA_Channel2_IRQNUM            147
#define  BDMA_Channel3_IRQNUM            148
#define  BDMA_Channel4_IRQNUM            149
#define  BDMA_Channel5_IRQNUM            150
#define  BDMA_Channel6_IRQNUM            151
#define  BDMA_Channel7_IRQNUM            152
#define  COMP1_IRQNUM                    153
#define  LPTIM2_IRQNUM                   154
#define  LPTIM3_IRQNUM                   155
#define  LPTIM4_IRQNUM                   156
#define  LPTIM5_IRQNUM                   157
#define  LPUART1_IRQNUM                  158
#define  CRS_IRQNUM                      160
#define  ECC_IRQNUM                      161
#define  SAI4_IRQNUM                     162
#define  WAKEUP_PIN_IRQNUM               165


#endif //!__STM32H743VIT6_IRQ_NUM_H__